The present invention relates to a semiconductor device and a process for fabricating the same, more specifically to a semiconductor device including capacitors and a process for fabricating the same.
A dynamic random access memory (DRAM) comprises memory cells each including one transfer transistor and one capacitor, which allows the DRAM to have a small area. This makes the DRAM a semiconductor device suitable for larger capacities. Because of the recent increased amounts of information processing of electronic devices, etc., DRAMS to be used in the electronic devices, etc. are required to be further micronized and have larger capacities. A DRAM having the cylindrical capacitors which will be described below are used.
A process for fabricating the conventional DRAM will be explained with reference to FIGS. 15A to 17. In FIGS. 15A to 17, the views on the left sides of the drawings are sectional views of the DRAM along a bit line, and sectional views of the DRAM along a word line are shown on the right sides of the drawings.
A device isolation film 112 is formed on the surface of a silicon substrate 110 by LOCOS (LOCal Oxidation of Silicon). Then, a gate oxide film (not shown) is formed on the surface of the silicon substrate 110. Next, a polysilicon film 114, a tungsten silicide film 116, a silicon oxide film 118, a silicon nitride film 120 and a silicon nitride oxide film 122 are sequentially formed on the entire surface by CVD (Chemical Vapor Deposition) to form a layer film 123 of these films.
Then, the layer film 123 is patterned into a prescribed shape to form gate electrodes 124 of the polycide structure of the polysilicon film 114 and the tungsten silicide film 116. The gate electrodes 124 function as the word lines also functioning as the gate electrodes of other transfer transistors extended vertically as viewed in the drawing on the left side of FIG. 15A.
Dopant ions are implanted in the silicon substrate 110 with the layer film 123 as a mask to form a source/drain diffused layer 126a, 126b by self-alignment with the layer film 123. Next, a silicon nitride film is formed on the entire surface and is subjected to anisotropic etching until the surfaces of the silicon substrate 110, the device isolation film 112 and the layer film 123 to form a sidewall insulation film 128 on the sidewalls of the layer film. The sidewall insulation film 128 is for forming an SAC (Self Aligned Contact) for ensuring a large margin for shift of the micronized contact. Then, an etching stopper film 130 of the silicon nitride film is formed on the entire surface.
Then, an inter-layer insulation film 132 of an about 0.5 μm-thickness BPSG (Boro-Phospho-Silicate Glass) film is formed by CVD. Then, the surface of the inter-layer insulation film 132 is planarized by reflow and CMP (Chemical Mechanical Polishing). Next, contact holes 134 for exposing the source/drain diffused layer 126b are formed by self-alignment with the sidewall insulation film 128. Then, conductor plugs 136a are formed in the contact holes 134 (see FIG. 5A).
Next, an about 0.1 μm-thickness silicon oxide film 138 is formed on the entire surf ace by CVD. Next, contact holes 140 for exposing the source/drain diffused layer 126a are formed by self-alignment with the sidewall insulation film 128. Then, a polysilicon film 142, a tungsten silicide film 144, a silicon oxide film 146, a silicon nitride film 148 and a silicon nitride oxide film 150 are sequentially formed by CVD on the entire surface to form a layer film 152 of these films. Then, the layer film 152 is patterned into a prescribed shape to form bit lines 154 of the polycide structure of the polysilicon film 142 and the tungsten silicide film 144 (FIG. 15B).
Next, a silicon nitride film is formed on the entire surface and is subjected to anisotropic etching until the surfaces of the silicon oxide film 138 and the layer film 152 are exposed, whereby a sidewall insulation film 156 is formed on the sidewalls of the layer film 152. Next, an inter-layer insulation film 160 is formed on the entire surface. Then, the surface of the inter-layer insulation film 160 is planarized by CMP. Then, an etching stopper film 161 of silicon nitride film is formed on the inter-layer insulation film 160 by CVD. Then, contact holes 162 for exposing the upper surfaces of the conductor plugs 136a are formed. Next, conductor plugs 136b are formed in the contact holes 162 (see FIG. 16A).
Next, an about 1.7 μm-thickness BPSG film 164 is formed on the entire surface by CVD. Then, openings 166 for exposing the upper surfaces of the conductor plugs 136b are formed in the BPSG film 164. The openings 166 are for forming storage electrodes 168 (see FIG. 17) of capacitors 179 in a later step (FIG. 16B).
Next, an about 0.05 μm-thickness polysilicon film is formed on the entire surface by CVD. Next, a resist film not shown is applied to the entire surface. Then, the polysilicon film and the resist film are polished by CMP until the surface of the BPSG film 164 is exposed. The storage electrodes 168 of the polysilicon film are formed inside the openings 166. Next, the BPSG film 164 is removed by HF-based wet etching with the etching stopper film 161 as a stopper.
Then, the resist film left on the inside of the storage electrodes 168 is removed by ashing. Next, an about 8 nm-thickness tantalum oxide film 172 is formed on the entire surface by CVD. The tantalum oxide film 172 functions as a dielectric of the capacitors 179. Next, a 0.05 μm-thickness titanium nitride film 174 and a 0.1 μm-thickness polysilicon film 176 are sequentially formed by CVD to form an opposed electrode 177 of the capacitors (see FIG. 17).
However, in the conventional DRAM fabrication process, when the BPSG film 164 is HF-based wet etching, it is often a case that the storage electrodes 168 are adversely peeled off the conductor plug 136b, or the etchant permeates near the upper surfaces of the conductor plugs 136b to adversely etch regions which should not be etched. This lowers yields of the DRAM.
In micronizing the DRAM it is necessary to increase a height of the capacitors so as to maintain substantially the same capacity of the capacitors. As a result, steps between each cell and its adjacent one is larger, which makes the formation of the contact holes and wirings difficult.
In the process for fabricating the conventional DRAM, a space must be ensured for the contacts between the gate electrodes of the transistors of peripheral circuits and the upper wirings, which hinders further micronization of the DRAM.
In the process for fabricating the conventional DRAM, the bit lines 154 are covered with a thick silicon nitride film of the high dielectric constant, which results in large parasitic capacities.